Senior Design Verification Engineer, Delhi - 1315834

Job Description

vDesign and develop test benches using HVL like SV – Develop verification environment components using HVL like System Verilog (VMM or UVM) or VERA – Generate verification and test plans – Develop test cases, execute and debug the design under test – As a design engineer should be able to develop design specs, HDL based RTL. Required knowledge and skills: – Good Logic and circuit design in Digital electronics, micro processor / controller concepts – VLSI Design flows – Expertise in HDLs (Verilog/VHDL) – Good communication skills Desirable Skills: – Familiarity with Scripting languages and a high level programming language