DFT and Physical Design, Bangalore - 1282217

Job Description

Requirements

Scan insertion & ATPG using Fastscan/TestKompress
Pattern Simulation with and without timing annotation & debugging simulation mismatches (VCS/Modelsim/NCSim).
Familiarity with WGL/STIL file formats.
Scan compression techniques.
Exposure to Memory BIST insertion tools (preferably LogicVision/Tessent)
Boundary Scan, JTAG concepts
Basic understanding of Tester requirements, basics of synthesis and timing. Exposure to SoC level DFT.

PD Engineer Job Description

Candidate is expected to work on RTL to GDSflow.
To be responsible for and own all aspects of physical design and physical verification efforts.

Requirements

Good knowledge of VLSI process and device characteristics, to make optimal trade-off between performance and power.
Good understanding of static timing analysis (STA), EM/IR and sign-off flows.
Strong hands-on experience with:
Synthesis, Floor planning, power planning, placement, timing optimization, clock tree synthesis.
Timing convergence using high speed design techniques with signal integrity & EM/IR.
Run equivalence checks across gates-to-gates as design progresses.
Physical design verification.
EDA Tool Expertise:
Encounter Digital Implementation System, PrimeTime-SI, StarXT, Calibre, Formality, Calibre.
Good scripting skills (perl, tcl).
Must have good communication skills and the ability and desire to work as part of a team.